The present invention relates to a method for forming a layer of an electrically conductive material filling a plurality of spaced apart recesses formed in the surface of a substrate, wherein the exposed upper surface of the layer is substantially coplanar with non-recessed areas of the substrate surface. More particularly, the invention relates to a method for performing xe2x80x9cback-endxe2x80x9d metallization of semiconductor high-speed integrated circuit devices having submicron design features and high conductivity interconnect features, which method facilitates planarization of the metallized surface by chemical-mechanical polishing (CMP), increases manufacturing throughput, and improves product quality.
The present invention relates to a method for forming metal films as part of metallization processing of particular utility in integrated circuit semiconductor device and circuit board manufacture, and is especially adapted for use in processing employing xe2x80x9cdamascenexe2x80x9d (or xe2x80x9cin-laidxe2x80x9d) technology.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized (e.g., 0.18 xcexcm), low RC time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced apart metallization layers are electrically connected by a vertically oriented conductive plug filling a via hole formed in the dielectric layer separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more levels of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type contemplated herein for use in e.g., xe2x80x9cback-endxe2x80x9d semiconductor manufacturing technology as required for fabrication of devices as above described typically comprise a metal such as titanium, tantalum, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. In use, each of the recited metals presents advantages as well as drawbacks. For example, aluminum (Al) is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid xe2x80x9cwetxe2x80x9d technology such as electrodeposition, step coverage with aluminum is poor when the metallization features are scaled down to submicron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, low dielectric constant materials, e.g., polyamides, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with aluminum.
The use of via plugs filled with tungsten (W) may alleviate several problems associated with aluminum. However, most W-based processes are complex and expensive. In addition, the high resistivity of W may cause Joule heating which can undesirably enhance electromigration of aluminum in adjacent wiring. Moreover, W plugs are susceptible to void formation and high contact resistance at the interface with the aluminum wiring layer.
Copper (Cu) and Cu-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large-scale integration (ULSI) devices requiring multilevel metallization systems for xe2x80x9cback-endxe2x80x9d processing of the semiconductor wafers on which the devices are based. Cu and Cu-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing aluminum and its alloys, as well as significantly higher resistance to electromigration. Moreover, Copper and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to aluminum and the refractory-type metals, copper and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
In addition to convenient, relatively low cost, low temperature, high throughput xe2x80x9cwetxe2x80x9d deposition by electroplating, copper and its alloys are readily amenable to low cost, high throughput electroless deposition of high quality films for efficiently filling recesses such as vias, contact areas, and grooves and trenches forming interconnection routing. Such electroless plating generally involves the controlled autocatalytic deposition of a continuous film of copper or an alloy thereof on a catalytic surface by the interaction in solution containing at least a copper salt and a chemical reducing agent, whereas electroplating comprises employing electrons supplied to an electrode from an external source (i.e., a power supply) for reducing copper ions in solution and depositing reduced metal atoms on the surface thereof. In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated for use herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
As indicated above, a commonly employed method for forming xe2x80x9cin-laidxe2x80x9d metallization patterns such as are required for xe2x80x9cback-endxe2x80x9d metallization processing of semiconductor wafers employs xe2x80x9cdamascenexe2x80x9d type technology. Generally, in such processing methodology, a recess (i.e., an opening) for forming, e.g., a via hole in a dielectric interlayer for electrically connecting vertically separated metallization layers, is created in the dielectric interlayer by conventional photolithographic and etching techniques, and filled with a metal plug, typically of tungsten. Any excess conductive material (i.e., tungsten) on the surface of the dielectric interlayer is then removed by, e.g., chemical-mechanical polishing techniques (CMP), wherein a moving pad is biased against the surface to be polished, with the interposition of a slurry containing abrasive particles (and other ingredients) therebetween.
A variant of the above-described technique, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Referring now to FIG. 1, schematically shown therein in simplified cross-sectional view is a conventional damascene processing sequence employing relatively low cost, high manufacturing throughput electroplating and CMP techniques for forming recessed xe2x80x9cback-endxe2x80x9d metallization patterns (illustratively of copper-based metallurgy but not limited thereto) in a semiconductor device formed in or on a semiconductor wafer substrate 1. In a first step, the desired arrangement of conductors is defined as a pattern of recesses 2 such as holes, grooves, trenches, etc., formed (as by conventional photolithographic and etching techniques) in the surface 4 of a dielectric layer 3 (e.g., a silicon oxide and/or nitride or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate 1. In a second step, a layer of copper or copper-based alloy 5 is deposited by conventional electroplating techniques to fill the recesses 2. In order to ensure complete filling of the recesses, the copper-containing layer is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer of excess thickness t so as to overfill the recesses 2 and cover the upper surface 4 of the dielectric layer 3. Next, the entire excess thickness t of the metal overburden layer 5 over the surface 4 of the dielectric layer 3 is removed by a CMP process utilizing an alumina-based slurry, leaving metal portions 5xe2x80x2 in the recesses 2 with their exposed upper surfaces 6 substantially coplanar with the surface 4 of the dielectric layer 3.
The above-described conventional damascene process forms in-laid conductors 5xe2x80x2 in the dielectric layer 3 while avoiding problems associated with other types of metallization patterning processing, e.g., blanket metal layer deposition, followed by photolithographic masking/etching and dielectric gap filling. In addition, such single or dual damascene-type processing can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, and with a plurity of metallization levels, i.e., five or more levels.
However, the use of electroplated metallization as described above has presented a number of problems, particularly, but not exclusively, with the use of copper-based metallurgy. For example, although electroplating of copper (a xe2x80x9cwetxe2x80x9d technique) has advantages over xe2x80x9cdryxe2x80x9d techniques (e.g., physical or chemical vapor deposition), such as rapid rates of deposition at low temperatures and good compatibility with xe2x80x9cwetxe2x80x9d CMP processing, it suffers from a drawback of ridge build-up over sharp corners of vias, grooves, and trenches. Thus, in conventional practices utilizing electrolytic deposition of copper or copper-based conductors, a rather thick blanket or overburden layer 5, typically about 0.5-1.5 xcexcm thick, must be deposited over the recess-patterned surface to ensure complete filling (i.e., overfilling) of recesses 2 such as via holes, trenches, grooves, and other variously configured openings. Moreover, the resulting surface after overfilling may be highly non-planar, with the layer thicknesses thereof spanning the entire range of thicknesses given above.
Removal of such thick, non-planar blanket layers of copper-based material in the subsequent CMP step for planarizing the interconnection metallization entails a number of disadvantages. For example, removal of the excess copper-based material by CMP is slow and expensive. Specifically, typical copper or copper alloy removal rates by CMP employing a conventional alumina-based slurry are on the order of about 2,000-3,000 xc3x85/min. Consequently, removal of 0.5-1.5 xcexcm thick copper-based layers can require long processing times extending up to about 5 minutes, considerably longer than that desired for good manufacturing throughput and reduced expense. In addition, removal of such thick as-deposited copper or copper-based blanket or overburden layers by CMP results in less uniform polished layers as are obtained when CMP is performed on thinner deposited layers. Such poor uniformity is generally accompanied by an increase in defects such as non-planarity (xe2x80x9cdishingxe2x80x9d) and gouging (xe2x80x9cerosionxe2x80x9d) between adjacent metallization lines.
A further drawback associated with copper-based xe2x80x9cback-endxe2x80x9d metallization is the possibility of copper diffusion into the underlying semiconductor, typically silicon, resulting in degradation of the semiconductive properties thereof, as well as poor adhesion of the deposited copper or copper alloy layer to various materials employed as dielectric interlayers, etc. As a consequence of these phenomena associated with copper-based metallurgy, it is generally necessary to provide an adhesion promoting and/or diffusion barrier layer intermediate the semiconductor substrate and the overlying copper-based metallization layer. Suitable materials for such adhesion/barrier layers include, e.g., chromium, tantalum, and tantalum nitride.
Yet another drawback associated with the use of electroplated copper or copper-based damascene type metallization arises from incomplete filling of the recesses during the electroplating process, resulting in void and/or other defect formation causing a reduction in device quality. Referring now to FIGS. 2A-2B and 3A-3B, wherein like reference numerals are employed as previously to designate like features, illustrated therein are simplified schematic cross-sectional views showing sequential phases of the filling of a damascene type recess 2 formed in a dielectric layer 3 overlying a semiconductor wafer substrate 1, typically monocrystalline silicon, with an electroplated metal layer 5, e.g., of copper or an alloy thereof. Referring more particularly to FIG. 2A, as illustrated therein, a thin adhesion/barrier layer 7 of chromium, tantalum, or tantalum nitride and an overlying thin nucleation/seed layer 8 of refractory metal, copper, or copper-based alloy have been sequentially deposited in conventional thicknesses (by conventional techniques such as PVD, CVD, and PECVD) over the surfaces of the dielectric layer exposed within recess 2 and the non-recessed surface 4.
Referring now to FIG. 2B, shown therein is a typical xe2x80x9cafter-platingxe2x80x9d view of recess 2, illustrating formation of an unfilled region 9 in the copper or copper alloy plug portion 5xe2x80x2 of metallization layer 5, which unfilled region constitutes an undesirable void or defect resulting in lowered device quality and performance characteristics. While the exact mechanism of such occlusion or xe2x80x9cpinching-offxe2x80x9d, of recess 2 at the upper, or mouth portion 2xe2x80x2, thereof is not known with certainty, it is believed to result from increased rates of copper electroplating at the corners of the nucleation/seed layer 8, e.g., at portions indicated by reference numeral 8A. It is further believed that such increased rates of deposition at corners 8A are related to the formation of higher electric fields at such corners during application of the electrical potentials necessary for effecting electroplating thereon.
The problem of recess occlusion or xe2x80x9cpinching-offxe2x80x9d during filling by copper electroplating is further exacerbated, when, as is illustrated in FIGS. 3A-3B analogous to FIGS. 2A-2B, the comers of the nucleation/seed layer 8 include overhanging portions 8B which are frequently formed as a result of conventional processing techniques (PVD, CVD, etc.) for forming same. Such overhang formation further constricts the opening dimension of the recess 2 at the mouth portion 2xe2x80x2 thereof and consequently increases the likelihood of xe2x80x9cpinch-offxe2x80x9d and concomitant void 9 formation.
As design rules for LSI, VLSI, and ULSI semiconductor devices extend further into the submicron range, e.g., about 0.18 xcexcm and below, and the number of metallization levels increases, the reliability of the metallization/interconnect pattern becomes increasingly critical. Accordingly, the problem of xe2x80x9cpinchng-offxe2x80x9d, or occlusion of recess openings during metal (e.g., copper or copper-based) filling thereof by electroplating requires amelioration.
Thus there exists a need for metallization process methodology enabling the formation of metal contact and interconnect members, particularly of copper or copper-based alloys, having high reliability, high yield, and high performance. In particular, there exists a need for eliminating the problem of void formation in metal recess-filling plugs which results when recesses are filled by conventional electroplating techniques.
The present invention addresses and solves the problems attendant upon conventional processes for manufacturing semiconductor devices utilizing electroplated copper metallization, particularly in the formation of in-laid xe2x80x9cback-endxe2x80x9d contacts/metallization patterns by damascene techniques employing electroplating and CMP for obtaining good manufacturing throughput and product quality.
An advantage of the present invention is a method of manufacturing a device with a highly reliable metallization pattern at lower cost and with higher manufacturing throughput than obtainable with conventional process methodology.
Another advantage of the present invention is a method of manufacturing an integrated circuit device utilizing copper-based xe2x80x9cback-endxe2x80x9d contacts and interconnections by a damascene process, with formation of highly reliable copper or copper alloy interconnect members having reduced incidence of defects such as voids therein.
Still another advantage of the present invention is a method for forming in-laid contacts and metallization patterns by electroplating and CMP techniques at an increased speed, lower cost, and with greater uniformity, planarity, and reliability than with conventional electroplating and CMP-based processes.
A further advantage of the present invention is an improved method for forming in-laid contacts and metallization patterns by a damascene-type electroplating and CMP-based process which is fully compatible with existing process methodology.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are achieved in part by a method of forming a layer of an electrically conductive material filling at least one recess formed in a substrate surface, which method comprises the sequential steps of:
providing a substrate having a surface comprising at least one recess formed therein, the recess comprising:
(a) a mouth surface portion at the upper end thereof and bordering an adjacent, non-recessed substrate surface portion;
(b) an interior wall surface portion; and
(c) a bottom surface portion at the lower end thereof;
providing an electrically conductive nucleation/seed layer over recess surface portions (a), (b), and (c), and extending over the adjacent, non-recessed substrate surface portion;
selectively rendering non-conductive exposed surfaces of the nucleation/seed layer formed over recess portion (a) and the adjacent, non-recessed substrate surface portion; and
filling the recess with a layer of an electrically conductive material by electroplating the layer on the nucleation/seed layer over recess surface portions (b) and (c), with no electroplating occurring on the surfaces of the nucleation/seed layer over recess surface portion (a) and the adjacent, non-recessed substrate surface portion rendered non-conductive;
whereby occlusion and/or pinching off of the recess mouth portion during the electroplating due to formation thereon of overhanging portions of the conductive material layer is prevented and unnecessary electroplating on non-recessed portions of the substrate surface is minimized.
In embodiments according to the invention, the substrate comprises a semiconductor wafer having a dielectric layer formed thereon and comprising the surface, the at least one recess formed therein comprises a plurality of recesses of different widths and/or depths for providing electrical contact areas, vias, interlevel metallization and/or interconnection routing of at least one active device region or component of the semiconductor wafer.
In other embodiments according to the present invention, the semiconductor wafer comprises monocrystalline silicon or gallium arsenide having integrated circuitry formed therein or thereon, the dielectric layer comprises an oxide and/or nitride of silicon or an organic polymeric material, the method further comprising planarizing the recess-filled surface by chemical-mechanical polishing (CMP).
In still other embodiments according to the present invention, the exposed surfaces of the nucleation/seed layer over recess surface portion (a) are selectively rendered non-conductive by (1) selective deposition thereon of a layer of an insulative material, as by use of a directed beam process, or (2) selective conversion into an insulative material, as by a directed oxidation process.
In further embodiments according to the present invention, the layer of electroplated electrically conductive material comprises a metal selected from the group consisting of copper, chromium, nickel, cobalt, gold, silver, aluminum, tungsten, titanium, tantalum, and alloys thereof, preferably copper or an alloy thereof, the nucleation/seed layer comprises a refractory metal, copper, or an alloy thereof, at least recess surface portions (a), (b), and (c) are provided with an adhesion promoting and/or diffusion barrier layer comprising chromium, tantalum, or tantalum nitride prior to providing the nucleation/seed layer thereon, and the copper or copper alloy recess-filled, metallized surface is planarized by CMP utilizing an alumina-based slurry.
Another aspect of the present invention is a method of manufacturing a semiconductor device, which method comprises the sequential steps of:
providing a substrate comprising a semiconductor wafer having thereon a dielectric layer with a surface comprising a plurality of spaced apart recesses formed therein, with non-recessed areas therebetween, each recess comprising:
(a) a mouth surface portion at the upper end thereof and bordering the adjacent, non-recessed substrate surface area;
(b) an interior wall surface portion; and
(c) a bottom surface portion at the lower end thereof;
providing an electrically conductive nucleation/seed layer formed over at least each of said recess surface portions (a), (b), and (c) and extending over the respective adjacent, non-recessed substrate surface area;
selectively rendering non-conductive exposed surfaces of the nucleation/seed layer formed over each surface portion (a)and respective adjacent, non-recessed substrate surface area; and
filling each recess with a layer of electrically conductive material by electroplating the layer on the nucleation/seed layer over respective recess surface portions (b) and (c), with no electroplating occurring on the surfaces of the nucleation/seed layer over recess surface portions (a) and respective adjacent, non-recessed substrate surface areas rendered non-conductive;
whereby occlusion and/or pinching off of the recess mouth portions (a) during electroplating due to formation thereon of overhanging portions of the conductive material layer is prevented and unnecessary electroplating on the respective non-recessed portions of the substrate surface is minimized.
According to yet another aspect according to the present invention, integrated circuit semiconductor devices comprising in-laid, xe2x80x9cback-endxe2x80x9d metallization patterns including recess mouth surface portions selectively rendered insulative according to the inventive method, are provided.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.